1. Field of the Invention
The present invention relates to a data transmitting and receiving system. More particularly, the present invention relates to a data transmitting and receiving system using an equalizer.
This application claims the benefit of Korean Patent Application No. 2006-69336, filed Jul. 24, 2006, the subject matter of which is hereby incorporated by reference.
2. Description of Related Art
Devices for inputting/outputting data are prone to errors (typically, referred to as “bit errors”) in the transmission of data caused, for example, by various random and systematic noise effects.
The frequency of bit errors in a data communication system may be expressed in terms of a “bit error rate (BER)”, which is the ratio of incorrectly received data bits relative to a total number of data bits received during predetermined period of time. For example, a data channel having a BER of 10−4 will receive an average of one incorrect (i.e., errant) data bit per every 104 data bits communicated through the channel. The BER of a given channel will vary with the speed of data transmission, channel length, and so on. Also, bit errors are mostly caused by noise in communication lines. Thus, a channel may be defined in its data communication capabilities by its inherent noise characteristics which determine most bit errors. In order to provide reliable data communication within contemporary systems, a data channel should have a BER in the order of 10−12 or lower.
As technology has developed, numerous techniques for eliminating or reducing noise have been proposed, but it remains practically impossible to completely eliminate all bit errors. Therefore, various error detection and/or correction codes are being conventionally employed to improve the performance of data channels. Of the many error detection/correction codes, one of the simplest and most widely-used is referred to as a cyclic redundancy checker (CRC).
A CRC method determines a check value for detecting bits errors in data received through a channel. More specifically, an initial CRC value is calculated in accordance with given data, added to the data, and transmitted from a transmitter. Thereafter, a new CRC value is calculated on the basis of the data actually received by a receiver at the other end of the channel. The initial CRC value and the new CRC value are compared within the receiver or a circuit associated with the receiver. When the two CRC values are determined to be different, bit error induced by noise in data channel are indicated. When an excessive or uncorrectable number of bit error(s) are detected, an error signal may be returned from receiver to the transmitter and data may be re-transmitted. Assuming that most of the bit errors apparent in the first data transmission are due to random noise effects, the re-transmission often results in effective data communication.
Systematic noise in a data channel, such as inter-channel crosstalk, inter-symbol interference (ISI), and simultaneous switching noise (SSN), poses a different set of considerations and implicates a number of different bit error detection and correction schemes. This is particularly true for high speed data communication systems.
Consider for example the block diagram of a conventional data transmitting and receiving system shown in FIG. 1. In FIG. 1, a transmission unit 10 includes a transmission controller 11, an error detection code generator 12, a parallel-serial converter 13, an output driver 14, a pre-emphasis controller 17, a receiving driver 18, and a re-transmission determiner 19.
A receiving unit 20 includes an input driver 21, a serial-parallel converter 25, a receiving controller 26, an error detector 27, a re-transmission requester 28, and a transmission driver 29.
Data channels (e.g., Ch, ChB, through ChR) communicate data between transmission unit 10 and receiving unit 20.
As transmission controller 11 outputs k-bits output data (dout), error detection code generator 12 generate s-bits error detection code (ec). Parallel-serial converter 13 receives the k-bits output data (dout) and s-bits error detection code (ec), converts them into a single serial stream of data, and outputs differential output data (do and doB) derived from the serial stream of data.
As illustrated, output driver 14 includes a transmission driver 15 and a pre-emphasis driver 16. Output driver 14 receives the differential output data (do and doB) and generates differential data signals (DO and DOB). In its operation, transmission driver 15 performs impedance-matching the received differential output data (do and doB) with channels (Ch and ChB), differentially amplifies this data, and outputs the amplified, differential output data. Pre-emphasis driver 16 modifies the differential output data (do and doB) in relation to a pre-emphasis control signal (pre_con) provided by pre-emphasis controller 17. Following pre-emphasis, the amplified differential output data (do and doB) are transmitted as data signals (DO and DOB). That is, output driver 14 combines the outputs of transmission driver 15 and pre-emphasis driver 16 to generate pre-emphasized data signals (DO and DOB) which are communicated over channels Ch and ChB.
Inevitably, the data signals (DO and DOB) are distorted during respective transmission over channels Ch and ChB to become errant data signals (DI and DIB). The degree and type of data distortions will vary by channel.
Input driver 21 includes a receiving driver 22 and a receiving equalizer 23. Input driver 21 performs impedance matching in order to receive as much of the errant data signals (DI and DIB) through the channels Ch and ChB as possible. In so doing input driver 21 prevents undesired signal reflections, corrects certain data distortions caused by transmission characteristics of channels Ch and ChB, and subsequently outputs differential input data (di and diB). Then, receiving equalizer 23 equalizes the differential input data (di and diB) in response to an equalization control signal (eq_con) provided by an equalizer controller 24.
The serial-parallel converter 25 converts the serially-provided differential input data (di and diB) into parallel-provided k-bits input data (din) subsequently communicated to receiving controller 26 and s-bits error detection code (ec) subsequently communicated to error detector 27 in addition to the k-bits input data (din).
Error detector 27 analyzes the input data (din) and the error detection code (ec) and derives an error signal (er) when there one or more bit error(s) are present in the input data (din).
In the illustrated example, receiving controller 26 ignores the input data (din) when it contains one or more bit error(s) (or more bit error than can be compensated at the receiver side). However, when the input data (din) is error free, receiving controller 26 proceeds forward with the indicated operation.
In response to the error signal (er) from error detector 27, re-transmission requester 28 generates an error indication data (edo) indicating a request for data re-transmission, and communicates this signal to transmission unit 10 via transmission driver 29 and data channel ChR. In this example, transmission driver 29 receives the error indication data (edo) and converts it into an error indication signal (EDO) in relation to the transmission characteristics of channel ChR.
In turn, the error indication signal (EDO) may become distorted into distorted error indication signal (EDI) during communication through the channel ChR.
Receiving driver 18 receives the distorted error indication signal (EDI), corrects the distortion, and outputs a corrected error indication signal (edi). In response to the corrected error indication signal (edi), re-transmission determiner 19 outputs a re-transmission signal (retry) to transmission controller 11 when re-transmission is necessary and allows transmission controller 11 to re-transmit the errantly received data.
In the above description, “pre-emphasis” refers to a method of pre-emphasizing the relatively higher frequency components of output data signals at the transmitter since such signal components tend to undergo disproportionate attenuation during transmission. The pre-emphasis control signal (pre_con) is used as an optimal pre-emphasis coefficient adapted to minimize inter-symbol interference (ISI) between data bits due to the unique channel transmission characteristics.
Similarly, receiving equalizer 23 is configured in consideration the unique transmission characteristics of the channel. The equalization control signal (eq_con) is used as an optimal equalization coefficient that enables maximum signal decoding.
In general, the pre-emphasis coefficient and the equalization coefficient are pre-set within a data transmitting and receiving system. In other words, the pre-emphasis coefficient and the equalization coefficient are determined in consideration of system characteristics including channel characteristics in order to optimize the data transmitting and receiving system against systematic noise, as opposed to random noise. Therefore, when receiving unit 20 detects an error in the input data (din) and subsequently outputs an error indication signal (EDO) to transmission unit 10, transmission unit 10 necessarily assumes that the error has been caused by random noise effects. If that assumption proves correct, it is expected that the randomly appearing noise will not be present during re-transmission. As a result, data may be re-transmitted under the in the belief that it will be communicated without error.
However, in practice it is not easy to optimize the pre-emphasis and equalization coefficients of the data transmitting and receiving system. Even if it were, the pre-emphasis and equalization coefficients often need to be changed under various circumstances. In order to change the pre-set coefficients, conventional data transmitting and receiving systems require re-initialization. For example, a conventional data transmitting and receiving system must stop transmitting data, enter a mode setting operation, and output test data related to the mode setting operation. As a result, the performance of the conventional data transmitting and receiving system deteriorates. In addition, the data transmitting and receiving system may still generate bit errors under changing circumstances in spite of periodically performed mode setting operations.